Shortest Explanation to NAND SR-flip-flop

When I was in high school studying electronics on my own as a hobby (it was not taught in the curriculum. No, physics people culturally hates electronics, they consider it a chore.), I followed the logic states of the bistable (two NAND gates) meticulously. However, it was tedious and hard to remember correctly.

There’s a fast way to reconstruct the explanation from scratch. You’ll need these invariants:

  • ‘1’ is ‘let the other input decide’ in AND logic (1 & A = A)
  • ‘0’ is ‘action‘ in AND logic, namely clear (0 & A = 0)
  • NAND is practically a NOT gate if you tie the inputs together
  • Two NOT gates chasing each other generates Q’ and Q
  • NAND gates provides a mean for external inputs to disturb the chasing NOT gates

By leaving external inputs (S and R) at ‘1’, we are letting the state pins decide, behaving like the two chasing NOT gates.

The only way to disturb the state is to create a ‘0’ (clear) action. The circuit is symmetric, so ‘S’ and ‘R’ is arbitrary as long as you are willing to switch the roles of Q and Q’.

  • Set Q to ‘0’ by sending a ‘0’ (clear action) through ‘S’
  • Set Q’ to ‘0’ by sending a ‘0’ (clear action) through ‘R’

There are no other valid actions in this configuration.

Side note: persisting the clear action will lead to 0 & 0 = 0 at the applied input and 1 & 1 = 1 at opposite NAND gate, which the achieved state remains. Normally we want to return the external inputs back to 1 to receive future commands (actions) correctly, both external inputs asserting low is invalid.

It’s more natural to have S and R being active high in transistor’s implementation. NAND’s ‘S’ and ‘R’ are active low (so technically, I should use S’ and R’ instead, but I’m following the more common nomenclature for the moment for the NAND gate implementation).

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